ANVIL documentation
How to size an amplifier with the ANVIL workbench, what each spec means, and what the results can and cannot tell you.
Getting started
- Open the workbench at /app/. There is no account and nothing to install.
- Use a current desktop version of Chrome, Edge, Firefox or Safari. The simulator is a WebAssembly build of ngspice, which every current browser supports.
- The first time you open the workbench, your browser downloads the simulator and the device models. Simulations then run inside the tab.
A run keeps your browser busy while it simulates. Leave the tab open until the run finishes.
A run, step by step
- Choose a topology. Select the 5T OTA or the two-stage Miller op-amp. The workbench builds the testbench for it.
- Enter specs. Enable the specs you care about and give each a min or max limit, and optionally a typical value for the optimizer to aim for. Choose the corners to check.
- Start the run. The workbench builds gm/Id tables from DC sweeps of the models and makes a hand-analysis first guess. A bounded Nelder-Mead optimizer then sizes the devices at the nominal corner, running an operating point, AC analysis, DC sweep and transient for each candidate. The best design is swept across every selected corner. If a spec fails at a corner, the optimizer refines against those corners and the nominal one, up to three rounds, keeping a refinement only if it improves worst-case compliance. The run screen shows each phase as it happens.
- Review. When the run ends, the compliance table grades each spec pass, marginal or fail at its worst corner. Open any value to see the netlist and the ngspice output behind it.
- Export. Download the netlist and the JSON report.
Supported topologies
Five-transistor OTA
An NMOS differential input pair with a PMOS current-mirror load and an NMOS tail current source, giving a single-ended output. It is the simplest amplifier that has a differential input, and its single high-impedance node makes it nearly a one-pole system with a comfortable phase margin. Its gain is limited to roughly one stage of intrinsic gain, so it suits moderate-gain uses such as buffers, comparator preamplifiers and bias loops.
The loop sizes the input pair, the mirror load and the tail device, and sets the tail current. The tail is biased from an NMOS diode fed by an ideal current reference.
Two-stage Miller op-amp
The 5T OTA as a first stage, followed by a PMOS common-source second stage with an NMOS current-source load. A Miller capacitor with a series nulling resistor, connected between the two stages, splits the poles, making the first-stage pole dominant and pushing the output pole beyond the unity-gain frequency. The second stage multiplies the gain and allows a wider output swing.
The loop sizes both stages and their bias devices, sets the bias currents, and chooses the compensation capacitor and nulling resistor. The trade-off it navigates is the usual one: more compensation buys phase margin at the cost of unity-gain bandwidth and slew rate.
Specs and how they are measured
Each spec is measured from a simulation of the testbench at one corner. The compliance table reports the worst value across all corners.
| Spec | Unit | Passes when | Definition |
|---|---|---|---|
| DC gain | dB | at least the min | Open-loop gain |Vout/Vin| at the first AC point (1 Hz), from an AC analysis around the operating point. |
| Unity-gain bandwidth | MHz | at least the min | Frequency at which the open-loop gain falls to 0 dB, interpolated on a log scale between AC points. |
| Phase margin | degrees | at least the min | 180° plus the unwrapped open-loop phase at the unity-gain frequency. |
| Power | µW | at most the max | Supply voltage times the DC supply current at the operating point, including the bias reference. |
| Slew rate | V/µs | at least the min | The slower of the rising and falling 20–80% output slopes of a unity-gain buffer driven by a 0.2 V input step, from a transient analysis. |
| Output swing | Vpp | at least the min | Output range over which the open-loop gain stays within 6 dB of its peak, from a DC sweep. |
Worst case means the lowest value for a spec with a min limit and the highest value for a spec with a max limit.
Corners
A corner is one combination of process, temperature and supply voltage. The default set has 45: five process corners (TT, FF, SS, FS, SF) at −40, 27 and 125 °C, each at the nominal 1.1 V supply and ±10%. You choose the corners in the setup screen, and the run screen shows how many are in the set.
The process corners are synthetic. They shift the threshold voltage of the predictive models by ±30 mV and scale mobility by ±8%. They are not foundry corners. Monte Carlo mismatch analysis is not part of the beta.
The optimizer works at the nominal corner. The best design is then simulated at every selected corner, and each spec is graded on its worst one.
Reading the results
Compliance table
One row per spec with its limits, the nominal value, the worst measured value, the corner where the worst value occurred, and a status:
- Pass: the worst value meets the limit with at least 5% headroom.
- Marginal: the worst value meets the limit with less than 5% headroom.
- Fail: the worst value misses the limit.
Headroom is measured relative to the limit. The 5% marginal band is the default and can be changed in the setup screen.
Every value is a link. Following it opens the artifact view: the netlist that was simulated, the ngspice log, the raw output, and a note on how the value was extracted.
Bode plot
Open-loop magnitude and phase of the final design versus frequency. The 0 dB crossing gives the unity-gain bandwidth, and the phase at that frequency gives the phase margin.
Sizing table
Width and length of every transistor in the final design, with its operating point, the bias settings and, for the two-stage op-amp, the compensation capacitor and nulling resistor.
When a run does not meet every spec
If the loop cannot meet every spec, the compliance table shows which ones fail and by how much at their worst corner. Specs that pull against each other, such as high bandwidth at very low power, may have no solution for the chosen topology under these models. Relax the tightest spec or try the other topology.
Exports
- Netlist. A standalone ngspice deck (.cir) with the TT model cards, the sized devices, the nominal AC testbench and its measurement checks.
- JSON report. The specs, the final device sizes, the operating point, the measured value of every spec at every corner with its artifact id and extraction note, the optimizer trace, engine and model details, and the compliance status, in a machine-readable file for scripts, reviews and records.
Both files are generated in your browser.
Models and their limits
ANVIL uses the FreePDK45 PTM 45 nm BSIM4 model cards: open predictive models that describe a plausible transistor at that node. They are not a foundry process design kit (PDK) and are not fitted to any foundry's silicon.
Use ANVIL results to choose a topology, understand trade-offs and get a starting sizing. Before tape-out, re-simulate and verify the design in your foundry's PDK with its own models, corners and sign-off flow.
What follows from using predictive models:
- Absolute numbers (gain, bandwidth, power) will differ from those of a real process at the same node. Trends and trade-offs carry over better than absolute values.
- The process corners are synthetic shifts of these models, not foundry corners, and there are no mismatch statistics or Monte Carlo runs.
- There is no noise analysis.
- There are no layout parasitics. Results are schematic-level.
- Bias comes from an ideal current reference.
- Device sizes are not checked against any foundry's design rules.
- The optimizer is a local search. It may not find the lowest-power design that meets the specs.
Questions
Do I need an account?
No. Open the workbench and use it.
Where do the simulations run?
In your browser, using ngspice compiled to WebAssembly. See the privacy policy for what data leaves your device.
Can I use my own PDK or another topology?
Not in the beta. Both are on the roadmap. To tell us which topology or process you need, get in touch.
How do I report a wrong result?
Email the JSON report and the netlist to hello@anvillab.tech with a line about what you expected. Those two files are enough to reproduce the run.